Digital-to-analog converters (DACs) are frequently used in the design of communication devices. By their design, however, DACs have inherent problems such as excess glitch energy upon a change in input voltage, settling problems immediately after the change in input voltage, and linearity problems related to the accuracy of an output voltage for a given input word. Each of these problems has its own effects on the performance of the communication device, specifically the spurious responses and intermodulation (IM) of signals resulting from the communication devices.
DACs are typically characterized by the number of bits that can be accepted at their input. Obviously, lower bit DACs (for example, 3-8 bit DACs) offer poor resolution, which consequently causes more distortion in the communication device. On the other hand, lower bit DACs are generally very fast and may exhibit fewer problems with respect to excess glitch energy and settling time. Higher bit DACs (10 to 16 bit DACs) offer better resolution (i.e., linearity performance) but are usually slow and may seriously suffer from the excess glitch energy/settling time problem. Consequently, when communication devices which are highly susceptible to the above-mentioned problems are designed, a severe compromise in the choice of DAC, and thus communication device performance, must be made.
Therefore, a need exists for a DAC which exhibits good excess glitch energy and settling performance while also exhibiting good linearity.